1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of Related Art
Patent Literature 1 discloses a process of forming gate trenches in active regions partitioned by device isolation regions with shallow trench isolation (STI).
By providing such trench gate electrodes in active regions, a trench gate type of metal insulator semiconductor (MIS) transistors can be formed.
In this case, active regions located on both sides of each trench gate electrode serve as a pair of impurity diffusion regions (source and drain regions). Furthermore, the gate electrodes in the gate trenches are formed with a line and space pattern (L/S pattern) so that they stride a plurality of active regions.    Patent Literature 1: JP-A 2010-232446